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AN1062 APPLICATION NOTE
Changing from the ST14xxx to the M14xxx IC EEPROM Memory Card Products in Your Application
STMicroelectronics IC EEPROM Memory Card products range from the low density ST14C02C (2 Kbit) up to the high density M14256 (256 Kbit). Near the middle of this range, the ST14xxx memories, fabricated using the low density technology, are being superseded by the corresponding M14xxx memories, fabricated using ST's high density technology. This document describes the main differences between memories fabricated in the two technologies, with the aim of helping the user to make the transition as smoothly as possible (in the application software and hardware) from the old family to the new one. The M14xxx devices have new features, over and above those previously supported. Not least, they are able to work up to an IC bus frequency of 400 kHz, with a power supply voltage value as low as 2.5 V. This document, therefore, is also aimed at helping the user to make optimum use of the new features of the new family. Table 1.
Device ST14C02C ST14C04C ST14E32 M14C04 M14C16 M14C32 M14C64 M14128 Memory Capacity 2 Kbit EEPROM (256 x 8) 4 Kbit EEPROM (512 x 8) 32 Kbit EEPROM (4K x 8) 4 Kbit EEPROM (512 x 8) 16 Kbit EEPROM (2K x 8) 32 Kbit EEPROM (4K x 8) 64 Kbit EEPROM (8K x 8) 128 Kbit EEPROM (16K x 8) Interface IC IC XIC IC IC XIC XIC XIC ST's Hi-Endurance Single Polysilicon CMOS technology which ST's Hi-Endurance Single Polysilicon CMOS technology Low density Fabrication Technology 1.2 m 1.2 m 1.0 m 0.6 m 0.6 m 0.6 m High density 0.6 m 0.6 m
guarantees an endurance well above one million erase/write cycles with a data retention of 40 years
ST's Hi-Endurance Double Polysilicon CMOS technology which
M14256
256 Kbit EEPROM (32K x 8)
XIC
guarantees an endurance well above 100,000 erase/write cycles with a data retention of 10 years
0.6 m
May 2000
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AN1062 - APPLICATION NOTE
Figure 1. ST14C02C IC EEPROM Memory Addressing
Start 1 0 1 0 0 0 0 R/W Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Parameters Range VCC 3V to 5.5V Cycling 1 million Data Retention 10 Years Contact 2 Not Connected Contact 8 MODE EEPROM Page size 8 bytes Bus Frequency 100 kHz Write Protection Not available
VCC
GND
SCL
SDA MODE
AI02491
Figure 2. ST14C04C IC EEPROM Memory Addressing
Start 1 0 1 0 0 0 A8 R/W Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Range VCC 3V to 5.5V Cycling 1 million Data Retention 10 Years Contact 2 PRE Contact 8 MODE EEPROM Page size 8 bytes Bus Frequency 100 kHz Write Protection Top Half of the memory using the PRE pad + Address Pointer
AI02456
Parameters
VCC PRE
GND
SCL
SDA MODE
Figure 3. M14C04 IC EEPROM Memory Addressing
Start 1 0 1 0 0 0 A8 R/W Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Range VCC 2.5V to 5.5V Cycling 1 million Data Retention 40 Years Contact 2 WC Contact 8 Not Connected EEPROM Page size 16 bytes Bus Frequency 400 kHz Write Protection Full memory using the WC pad
AI02168
Parameters
VCC WC
GND
SCL
SDA
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AN1062 - APPLICATION NOTE
Figure 4. M14C16 IC EEPROM Memory Addressing
Start 1 0 1 0 A10 A9 A8 R/W Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Range VCC 2.5V to 5.5V Cycling 1 million Data Retention 40 Years Contact 2 WC Contact 8 Not Connected EEPROM Page size 16 bytes Bus Frequency 400 kHz Write Protection Full memory using the WC pad
AI02168
Parameters
VCC WC
GND
SCL
SDA
Figure 5. ST14E32/ST15E32 XIC EEPROM Memory Addressing
Start 1 0 1 0 0 0 0 R/W Ack A15 A14 A13 A12 A11 A10 A9 A8 Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Range VCC 2.7V to 5.5V Cycling 100,000 Data Retention 10 Years Contact 2 WC Contact 8 Not Connected EEPROM Page size 32 bytes Bus Frequency 400 kHz Write Protection Full memory using the WC pad
AI02168
Parameters
VCC WC
GND
SCL
SDA
Figure 6. M14C32 XIC EEPROM Memory Addressing
Start 1 0 1 0 0 0 0 R/W Ack A15 A14 A13 A12 A11 A10 A9 A8 Ack A7 A6 A5 A4 A3 A2 A1 A0 Ack ..... Range VCC 2.5V to 5.5V Cycling 1 million Data Retention 40 Years Contact 2 WC Contact 8 Not Connected EEPROM Page size 32 bytes Bus Frequency 400 kHz Write Protection Full memory using the WC pad
AI02168
Parameters
VCC WC
GND
SCL
SDA
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AN1062 - APPLICATION NOTE
SIGNAL DESCRIPTION Serial Clock (SCL) Available on all the standard IC devices, this signal is used to synchronize all data in and out of the device. A pull up resistor can be connected from Serial Clock (SCL) to VCC. Serial Data (SDA) Available on all the standard IC devices, this signal is bi-directional, and is used to transfer data in and out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V CC. Figure 7. ST14C04C Write Protection
1FFh
ADDRESS POINTER PROTECTED AREA
100h Max
000h
AI03775
Protect Enable (PRE) This signal is available on the ST14C04C only, and is not provided on the new M14xxx memories. The Block Address Pointer byte (as shown in Figure 7) is used to point to a page of memory. All the memory locations in this page, and above, are write-protected when bit b2 (Protect Flag in location 1FFh) is reset to 0, and Protect Enable (PRE) is driven High (PRE=V IH). To unprotect, PRE is held at VIL. This mechanism allows from 8 to 256 bytes of the top of the memory to be write-protected. The bottom of the memory cannot be write-protected. (Please see the ST14C04C data sheet, and the AN1006 application note, for more details). Mode (MODE) The MODE input is available on the ST14C02C and ST14C04C, and is not provided in the new M14xxx memories. This input is used to select between the Multibyte Write mode (MODE=VIH) and the Page Write mode (MODE=VIL). Figure 8. Wrap-round in Page Write Mode and Multibyte Write Mode
Page Write Mode
Multibyte Write Mode
AI03776
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AN1062 - APPLICATION NOTE
In Page Write mode, it is possible to write from 1 to 8 bytes in one programming cycle, assuming that all writes are to the same physical row of memory. An attempt to write beyond the end of the row causes the address to wrap round to the beginning of the same row, as shown in the left half of Figure 8, and not to increment to the next row, as might have been expected. In Multibyte Write mode, it is possible to write from 1 to 4 bytes. This time, though, the address register is incremented to the start of the next row after writing to the end of the current row, as shown in the right half of Figure 8. However, the cost of doing this is to increase the programming time. If all writes are within a single row of memory, the instruction is executed in one programming cycle. If the row boundary is crossed, though, the instruction is executed in two programming cycles (one programming cycle for each row). When unconnected, the MODE input is internally read as a V IH (Multibyte Write mode). The MODE pin is treated as Don't Care for the Byte Write mode. Write Control (WC) The Write Control input is available on the M14C04, M14C16, ST14E32 and M14C32. This is the standard use of the C2 module pad, according to ISO 7813, and is used for all the M14xxx IC EEPROM products. The Write Control input is used to enable (WC=VIL) or inhibit (WC=VIH) writing to the entire memory area. When left unconnected, the WC input is internally read as V IL and write operations are allowed. AC PARAMETERS The same IC specifications are used for both ST14Cxx and M14xxx EEPROM family products. Two IC standards are available, depending on the bus frequency: one specified at 100 kHz and one at 400 kHz (see Table 2). Note that a product specified at 400 kHz is backward compatible with the 100 kHz specification. The main significance of this is in respect of the differences in the rise times for the two specifications. Table 2. IC timings specifications
Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL2 tCHDX tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tW Alt. tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Parameter Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time Clock Frequency Write Time 200 400 10 20 20 600 600 600 0 1300 100 600 1300 1000 200 100 10 Fast IC 400 kHz Min. Max. 300 300 300 300 20 20 4700 4000 4000 0 4700 250 4000 4700 3500 IC 100 kHz Min. Max. 1000 300 1000 300 Unit ns ns ns ns ns ns ns s ns ns ns ns ns ns kHz ms
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AN1062 - APPLICATION NOTE
MEMORY REPLACEMENT Converting from Using the ST14C02C or ST14C04C to the M14C04 The replacement, in an application, of a ST14C02C or a ST14C04C by a M14C04 is straightforward under the following conditions: - If the application does not currently use the Multibyte Write mode of the ST14Cxx, and has the MODE pin connected to GND. - If the application does not currently use the Protect Enable feature of the ST14C04C, and has the PRE pin connected to GND, or left floating. - If the application software does not currently use the Page Write roll-over feature of the ST14Cxx. (As the page size is different between the ST14Cxx and the M14C04, data will not be written at the right locations). Converting from Using the ST14E32 to the M14C32 The ST14E32 and the M14C32 are fully compatible. They have the same pin out, the same page size and can both work at 400 kHz. Converting from Using One Member of the M14xxx family to Another All members of the new M14xxx IC EEPROM family have standardized on the pin outs shown in Figure 9. Thus, upgrading from one member of the family to another is particularly straightforward. Moreover, they all off the same VCC range (2.5 V to 5.5 V) and the same I2C bus frequency (400 kHz). Figure 9. M14xxx Module Pin Out
VCC WC
GND
VCC WC
GND
SCL
SDA
SCL
SDA
AI02168
AI02204
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AN1062 - APPLICATION NOTE
If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:
apps.memcard@st.com ask.memory@st.com
(for application support) (for general enquiries)
Please remember to include your name, company, location, telephone number and fax number.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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